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ab-1205-5 4 port cascadeable 100base and atm repeater hub product specification ab-1205-5 4-port 100basetx repeater
- 2 - rev 1.4 copyright ? copyright 1997 ab semicon limited. all rights reserved. no part of this publication may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language or any computer language, in any form or by any third party, without the prior written permission of ab semicon limited. disclaimer ab semicon limited reserves the right to revise this publication and to make changes from time to time to the contents hereof without obligation to notify any person or organization of such revision or changes. ab semicon limited has endeavoured to ensure that the information in this publication is correct, but will not accept liability for any error or omission. ab semicon AB1205-5 100base and atm repeater hub product specification
rev 1.4 - 3 - ab-1205-5 100base and atm 4 port repeater features: * 4 ports for or amd's fddi chip sets and gec?s nwk914 * local bi-directional high-speed bus for daisychaining * compatible with 100base tx, t4 and t6 * compatible with 100base vg * 80 pin pqfp package * low power c-mos technology 0.8micron
- 4 - rev 1.4 introduction this repeater chip allows the connection of an amd 79865 and 79866 chipset together with nsm dp83223 as the physical layer chip as well as being able to use the gec nwk 914 or ab semicon ab10100phy which can replace the amd and national chip set giving a maximum in flexibility. it can process 4 ports simultaneously in half duplex. the encryption and decryption circuit is built into each of the channels. a local bus allows daisychaining of any number of devices. chip structure the chip contains four high-speed 5bit channels and the control logic for the physical layer interface. each channel has its own encryption and decryption circuit for circuit simplicity and reduced emi. error arbitration logic and collision detection which is also available on output pins on the chip which are capable of driving leds directly. there are additional led outputs to indicate tx or rx data. figure 1 functional block diagram tx-1 output tx-2 output tx-3 output tx-4 output idle detect priority packet switch logic & idle byte insertion for active channel rx-3 input rx-2 input rx-4 input ring buffer note: daisychain control and data i/o are only functional on ab-1205-5 packet management logic and timers ring buffer ring buffer ring buffer global reset d aisychain control in/out led output daisychain in/output cypherstream decryption cypherstream decryption cypherstream decryption cypherstream encryption cypherstream encryption cypherstream encryption rx-1 input cypherstream decryption cypherstream encryption
rev 1.4 - 5 - applications the chip can be used in many different applications where random encryption and decryption is required to achieve a semi spread spectrum use of copper wire to reduce rfi emitted from the cable. it is most powerful for repeater devices such as 4, 8 or 16 port or any multiple of 4 ports, hub devices. such applications include 100basetx repeaters. figure 2 gives an overview of low cost repeater applications for which this chip is suitable. such a repeater can be used in workgroup or server- based environments. the data is fully transparently distributed through the network. example for a 4 port repeater figure 3 shows a 4 port repeater with an extension connector to daisychain any number of 4 port repeaters. 100basetx laserprinter 100basetx workstation 100basetx fileserver 100basetx repeater hub am 79866 dp 83223 magnetics 12 way daisychain connector (ab-1205-5 only) tx rx tx rx rj 45 connector tx rx rj 45 connector tx rx xtal osc ~ ? rj 45 connector ? ? ? am 79865 ? ab-1205-1 or ab-1205-5 4-port repeater magnetics rj 45 connector figure 3 figure 2
- 6 - rev 1.4 fig 6. connection of ab10/100phy to AB1205-5 interconnection of AB1205-5 and ab10100phy physical layer the diagram below shows how the signals between AB1205-5 and ab10100phy are interconnected for a single port. this interconnection is repeated for the remaining 3 ports, please also refer to the ab10100phy product specification. ? ? ? 1:1 m a g n e t i c s rj45 15 w 68 w 15 w 50 w 50 w 0.1 m f 620 w txv cc .033 m f 1k w 100pf xial osc. 5 5 0.1 m f 6.2k w ab 1205-5 pcs or mac (with embedded pcs) lfta refclk tdat0-4 txc rxc rdat0-4 lfra lfr8 lft8 txref txgnd txop txon rxip rxin ab 10/100 phy
rev 1.4 - 7 - clock distribution circuit the following diagram shows how the clock is distributed. to assure that the clock is arriving at the same time on all channels, a ? 244 is used to re-shape the clock signal for each channel. diagram showing clock distribution note: when daisychaining the AB1205-5 the remaining buffers of the ? 244 may be used to re-generate the clock signal. 2 4 6 8 11 13 15 17 rx2in0 tx2out4 1 19 r10 24r t x 2 o u t 2 31 32 33 34 35 77 76 18 16 14 12 9 7 5 3 lsclk lsclk lnkok2 rsclk2 12 12 12 12 12 12 12 12 lnkok2 12 12 12 12 12 rx2in(0..4) tx2in(0..4) 1y1 1y2 1y3 1y4 2y1 2y2 2y3 2y4 x x x x x rx2in0 rx2in1 rx2in2 rx2in3 rx2in4 tx2out4 tx2out3 tx2 out2 tx2 out1 tx2 out0 t x 2 o u t 1 t x 2 o u t 0 r13 24r shield power & ground 1a1 1a2 1a3 1a4 2a1 2a2 2a3 3a4 r14 10k vcc gnd vcc gnd 25mhz c11 100nf 50v 29 rx2in1 rx2in2 rx2in3 rx2in4 tx2out3 r x 2 i n(0..4) tx2in(0..4) ?244 AB1205-5 rsclk2 AB1205-5 ab10100 phy
- 8 - rev 1.4 reset circuitry for ab-1205-5 the following diagram shows the reset circuit for the ab-1205-5 four port and cascadeable hub chip. ______ reset ab-1205-5 rx_busy_0 disab(1) collision relay daisy<4> daisy<3> daisy<2> daisy<1> daisy<0> as244/1 as244/2 osc~ 25mhz pin 53 to other devices ab-1205-5 ab-1205-5 60 61 63 64 65 57 55 60 61 63 64 65 57 55 54 54 reset circuit for ab-1205-5 daisychaining the ab-1205-5
rev 1.4 - 9 - thermal characteristics for AB1205-5 this device is supplied in a plastic quad flat pack with a pin count of 80. in this configuration, it has a thermal resistance (0 ja - junction-to-ambient measurement) of 85 c/w in an alloy 42 lead frame with a value of 68 c/w in a copper lead frame. as this device is currently supplied in the alloy lead frame, only that figure has been used in the following calculations. the power dissipation (pd) of the device is calculated as follows: pd + t j - t a 0 ja thus the power dissipation is 1.2 watts at an ambient of 25 c and 650 mw at 70 c. the following plot shows the variation of power dissipation with ambient: power dissipation of AB1205-5 typical 300mw a value of t j max of 125 c was used. the range of t j is -40 to 125 c. 1.6 - 1.4 - 1.2 - 1 - 0.8 - 0.6 - 0.4 - 0.2 - 0 - -20 - -10 - 0 - 10 - 20 - 30 - 40 - 50 - 60 - 70 - 80 - 90 - 100 - 110 - 120 - 125 - 130 - 140 - pd ta 1234567890123456789012345678901212345 1 23456789012345678901234567890121234 5 1 23456789012345678901234567890121234 5 1 23456789012345678901234567890121234 5 1 23456789012345678901234567890121234 5 1 23456789012345678901234567890121234 5 1234567890123456789012345678901212345 AB1205-5 typical recommended area of operation maximum ambient temperature
- 10 - rev 1.4 packaging information 3.07 0.35 2.72 23.20 20.00 17.20 14.00 0.75 0.80 0.35 24 16 2.82 0.25 2.57 23.00 19.90 17.00 13.90 0.65 0.25 3.32 0.45 287 23.40 20.10 17.40 14.10 0.95 0.45 80 lead min. nom. max. d d1 ee1 p a2 a1 b l pin 1 a number of pins nd number of pins ne a a1 a2 d d1 e e1 l p b nd ne
rev 1.4 - 11 - pin id signal designator i/o pin assignment 1 gnd ground 2nc 3nc 4 output tx3_out3 5 output tx3_out4 6 output tx4_out0 7 vcc power 8 output tx4_out1 9 output tx4_out2 10 output tx4_out3 11 output tx4_out4 12 output -link4-(led) 13 output -led3-(led) 14 output -link2-(led) 15 output -link1-(led) 16 output -rec4-(led) 17 output -rec3-(led) 18 output -rec2-(led) 19 gnd ground 20 output -rec1-(led) 21 input linkok1 22 input rsclk1 23 vcc power 24 input rx1_in0 25 input rx1_in1
- 12 - rev 1.4 pin id signal designator i/o pin assignment 2 6 input rx1_in2 27 input rx1_in3 28 input rx1_in4 29 input linkok2 30 input rsclk2 31 input rx2_in0 32 input rx2_in1 33 input rx2_in2 34 input rx2_in3 35 input rx2_in4 36 input -linkok3- 37 input -rsclk3- 38 input rx3in0 39 input rx3in1 40 input rx3in2 41 input rx3in3 42 vdd power (core) 43 gnd ground 44 input rx3in4 45 input -linkok4- 46 gndc ground (core) 47 input rsclk4 48 input rx4_in0 49 input rx4_in1 50 input rx4_in2
rev 1.4 - 13 - i/o pin assignment pin id signal designator 51 input rx4_in3 52 input rx4_in4 53 input -reset- 54 input lsclk 55 output -disab1-(col) 56 n/c n/c 57 input/output rx_busy_0 58 vcc power 59 gnd ground 60 input/output daisy 0 61 input/output daisy 1 62 vcc power 63 input/output daisy 2 64 input/output daisy 3 65 input/output daisy 4 66 gnd ground 67 output tx1_out0 68 output tx1_out1 69 output tx1_out2 70 output tx1_out3 71 output tx1_out4 72 output tx2_out0 73 output tx2_out1 74 vcc power 75 output tx2_out2
- 14 - rev 1.4 clock to pcolrx inactive at end of collided packet pin id signal designator i/o pin assignment 7 6 output tx2_out3 77 output tx2_out4 78 output tx3_out0 79 output tx3_out1 80 output tx3_out2 /dataen <4> st0 /dataen <3> st0 /dataen <2> st0 /dataen <1> st0 1>,/ptxdat<0> 1f /prxbsy st0 /pcolrx st0 /pcol st0 /plsclk st1 time in ns 00 1f 1f 1f x 1f 1f 15 20 10 5
rev 1.4 - 15 - clock to pcolrx and pcol active when a collision occurs /dataen <4> st1 /dataen <3> st1 /dataen <2> st0 /dataen <1> st0 1>,/ptxdat<0> 03 /prxbsy st0 /pcolrx pu1 /pcol hiz /plsclk st1 time in ns 03 02 03 03 04 03 x x 00 10 5 15 10 5 clock to prxbsy high and byway data disable at end of packet /dataen <4> st0 /dataen <3> st0 /dataen <2> st0 /dataen <1> st0 1>,/ptxdat<0> 1f /prxbsy st0 /pcolrx pu1 /pcol hiz /plsclk st1 time in ns 1f x 1f 1f 1f 1f 00 5 10 20 15 5
- 16 - rev 1.4 clocking of byway data clock to prxbsy low and by way data enable at beginning of packet /dataen <4> st0 /dataen <3> st0 /dataen <2> st0 /dataen <1> st1 1>,/ptxdat<0> 1f /prxbsy pu1 /pcolrx pu1 /pcol hiz /plsclk st1 time in ns 1f 1f x 10 00 5 10 5 /dataen <4> st0 /dataen <3> st0 /dataen <2> st0 /dataen <1> st1 1>,/ptxdat<0> 0e /prxbsy st0 /pcolrx pu1 /pcol hiz /plsclk st0 time in ns 10 x 10 00 0f 0e 0f 0e 0f 5 15 5
rev 1.4 - 17 - beginning of packet (1 channel starts transmission) /dataen <4> st0 /dataen <3> st0 /dataen <2> st0 /dataen <1> st1 1>,/ptxdat<0> 1f /prxbsy st0 /pcolrx pu1 /pcol hiz /plsclk st1 time in ns 10 00 09 x 08 x 07 x 06 x 05 x 04 x 03 x x 1f x 02 1f 00 01 x x 5 5 10 15 end of packet (1 channel ends transmission) /dataen <4> st0 /dataen <3> st0 /dataen <2> st0 /dataen <1> st0 1>,/ptxdat<0> 1f /prxbsy pu1 /pcolrx pu1 /pcol hiz /plsclk st1 time in ns x 1f 1f xx x x x xx x x 01 x x 1f 06 02 03 05 04 x 1f 1e 1d 1c x 1a 1b 00 10 15 20 25 5 5
- 18 - rev 1.4 end of collision (the collided channels ceased transmission) /dataen <4> st0 /dataen <3> st0 /dataen <2> st0 /dataen <1> st0 1>,/ptxdat<0> 1f /prxbsy pu1 /pcolrx pu1 /pcol hiz /plsclk st1 time in ns 1f x x x x xx x 0c x x 0a 09 08 x 07 10 15 20 25 5 5 x 1f 1f 1f 0e x 0d 0b 1f 00 /dataen <4> st0 /dataen <3> st0 /dataen <2> st0 /dataen <1> st0 1>,/ptxdat<0> 1f /prxbsy pu1 /pcolrx pu1 /pcol hiz /plsclk st1 time in ns 10 15 20 25 5 5 x 1f 1f xx x x x x xx x x x x x 06 07 09 04 03 01 0b 0a 08 05 02 00 1f 00 beginning of collision (two channels try to transmit simultaneously)
rev 1.4 - 19 - vcc +5v 10% vdd (core) +5v 10% icu 50 ma (typical) 60 ma (max) gnd and gndc 0v input - low < 0.7v input - high 3 1.8v output - low < 0.6v output - high 3 2.6v input - load 5 gates lsclk 25 mhz operating temperature: range 0 c - 70 c humidity 90% (non condensing) storage temperature: range -10 c - +80 c humidity 95% (non condensing) product has to be used within 6-7 hours after unpacking. electrical specification
distributed in japan rikei corporation 1-26-2 nishi-shinjuku shinjuku-ku tokyo 163-05 japan tel: +81 3 3345 2189 fax: +81 3 3344 3949 ab semicon limited ab semicon house 62 victoria road burgess hill west sussex rh15 9lh tel: +44 1444 870408 fax: +44 1444870452 www.ab-semicon.com ab semicon inc. 8305 highway 71 west austin texas 78735 usa tel: +1 512 288 6750 fax: +1 512 288 7676

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